/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T1 Processor File: address.h
* Copyright (c) 2006 Sun Microsystems, Inc.  All Rights Reserved.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
* 
* The above named program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public
* License version 2 as published by the Free Software Foundation.
* 
* The above named program is distributed in the hope that it will be 
* useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
* General Public License for more details.
* 
* You should have received a copy of the GNU General Public
* License along with this work; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
* 
* ========== Copyright Header End ============================================
*/
/*
 * Copyright (c) 2001 by Sun Microsystems, Inc
 */

#ifndef _ADDRESS_H
#define _ADDRESS_H


#define BUS(n)		((n) << 16)
#define DEV(n)		((n) << 11)
#define FUN(n)		((n) << 8)

#define CONFIG_ADDR(b,d,f)	\
	{ PCI_ADDR_CONFIG|BUS(b)|DEV(d)|FUN(f), 0x0, 0x0, 0x0, 0x0 }

#define MEMORY_ADDR(b,d,f,a,s)	\
	{ PCI_RELOCAT_B|PCI_ADDR_MEM32|BUS(b)|DEV(d)|FUN(f), 0x0, (a), 0x0, (s) }

#define MEMORY_ADDR_BOOTBUS(b,d,f,a,s)  \
        { PCI_RELOCAT_B|PCI_ADDR_MEM32|BUS(b)|DEV(d)|FUN(f)|0x10, 0x0, (a), 0x0, (s) }

#define SCHIZO_INTR(n)		((n) | (SCHIZO_IO_SAFARI_PORTID << 6))
/*
 device:		vaddr:		end:		size:
 SAFARIBASE_VADDR	0xff400000	0xffc00000	0x800000

 DISKA0_VADDR		0xffe00000			0x20


 DISKA1_VADDR		0xffe02000
 DISKA2_VADDR		0xffe04000
 DISKA3_VADDR		0xffe06000
 DISKA4_VADDR		0xffe08000
 DISKA5_VADDR		0xffe0a000
 DISKA6_VADDR		0xffe0c000
 DISKA7_VADDR		0xffe0e000
 DISKA8_VADDR		0xffe10000
 DISKA9_VADDR		0xffe12000
 DISKA10_VADDR		0xffe14000
 DISKA11_VADDR		0xffe16000
 DISKA12_VADDR		0xffe18000
 DISKA13_VADDR		0xffe1a000
 DISKA14_VADDR		0xffe1c000
 DISKA15_VADDR		0xffe1e000
 DISKA16_VADDR		0xffe20000
 DISKA17_VADDR		0xffe22000
 DISKA18_VADDR		0xffe24000
 DISKA19_VADDR		0xffe26000
 DISKA20_VADDR		0xffe28000
 DISKA21_VADDR		0xffe2a000
 DISKA22_VADDR		0xffe2c000
 DISKA23_VADDR		0xffe2e000
 DISKA24_VADDR		0xffe30000

 DISKB0_VADDR		0xffe80000
 DISKB1_VADDR		0xffe82000
 DISKB2_VADDR		0xffe84000
 DISKB3_VADDR		0xffe86000
 DISKB4_VADDR		0xffe88000
 DISKB5_VADDR		0xffe8a000
 DISKB6_VADDR		0xffe8c000
 DISKB7_VADDR		0xffe8e000
 DISKB8_VADDR		0xffe90000
 DISKB9_VADDR		0xffe92000
 DISKB10_VADDR		0xffe94000
 DISKB11_VADDR		0xffe96000
 DISKB12_VADDR		0xffe98000
 DISKB13_VADDR		0xffe9a000
 DISKB14_VADDR		0xffe9c000
 DISKB15_VADDR		0xffe9e000
 DISKB16_VADDR		0xffea0000
 DISKB17_VADDR		0xffea2000
 DISKB18_VADDR		0xffea4000
 DISKB19_VADDR		0xffea6000
 DISKB20_VADDR		0xffea8000
 DISKB21_VADDR		0xffeaa000
 DISKB22_VADDR		0xffeac000
 DISKB23_VADDR		0xffeae000
 DISKB24_VADDR		0xffeb0000



 PBM_A_CONFIG_VADDR	0xfff00000	0xfff08000	0x8000
 PBM_B_CONFIG_VADDR	0xfff08000	0xfffc0000	0x8000

 PCISIMC_VADDR		0xfffc0000			0x2000

 RTC_VADDR		0xfffc2000			0x2000
 */
#define	SCHIZO_NID_SHIFT		25
#define	SCHIZO_AID_SHIFT		20
#define	SCHIZO_AID			0x0000000001F00000ULL
#define SCHIZO_CSR_OFFSET		0x410000 
#define SCHIZO_IOMMU_CSR_OFFSET		0x0200
#define SCHIZO_IOMMU_TSB_OFFSET		0x0208
#define SCHIZO_IOMMU_FAR_OFFSET		0x0210
#define SCHIZO_IOMMU_TAG_OFFSET		0xA580
#define SCHIZO_IOMMU_DATA_OFFSET	0xA600
#define SCHIZO_SBUF_CSR_EN		0x0000000000000001ULL
#define SCHIZO_SBUF_CSR_DE		0x0000000000000002ULL
#define SCHIZO_SBUF_CSR_OFFSET		0x2800
#define SCHIZO_SBUF_TAG_OFFSET		0xBA00
#define SCHIZO_SBUF_DATA_OFFSET		0xBB00

#define SCHIZO_PADDR		0x4000f800000ULL


/* schizo's hack */
#define SAFARIBASE_PADDR	SCHIZO_PADDR
#define SAFARIRGN_RSIZE		0x800000
#define SAFARIBASE_VADDR	0xFF400000

/* pci bus b config address */
#define	SCHIZO_PBM_B_CONFIG_PADDR	0x40200000000ULL
#define	SCHIZO_PBM_B_CONFIG_PADDR_MATCH	0x8000040200000000ULL
#define SCHIZO_PBM_B_CONFIG_PADDR_MASK	0x7ffff300000ULL

/* pci bus b io address */
#define SCHIZO_PBM_B_IO_PADDR		0x40201000000ULL

/* pci bus b mem address */
#define	SCHIZO_PBM_B_MEM_PADDR		0x60000000000ULL
#define	SCHIZO_PBM_B_MEM_PADDR_MATCH	0x8000060000000000ULL
#define SCHIZO_PBM_B_MEM_PADDR_MASK	0x7ff80000000ULL

/* pci bus a config address */
#define	SCHIZO_PBM_A_CONFIG_PADDR	0x40202000000ULL
#define	SCHIZO_PBM_A_CONFIG_PADDR_MATCH	0x8000040202000000ULL
#define SCHIZO_PBM_A_CONFIG_PADDR_MASK	0x7fffe000000ULL

/* pci bus a io address */
#define SCHIZO_PBM_A_IO_PADDR		0x40203000000ULL

/* pci bus a mem address */
#define	SCHIZO_PBM_A_MEM_PADDR		0x60100000000ULL
#define	SCHIZO_PBM_A_MEM_PADDR_MATCH	0x8000060100000000ULL
#define SCHIZO_PBM_A_MEM_PADDR_MASK	0x7ff80000000ULL

/* 25 disks on bus A */
#define DISKA0_PADDR	SCHIZO_PBM_A_MEM_PADDR + DISKA0_OFFSET


#define DISKA1_PADDR	SCHIZO_PBM_A_MEM_PADDR + DISKA1_OFFSET
#define DISKA2_PADDR	SCHIZO_PBM_A_MEM_PADDR + DISKA2_OFFSET
#define DISKA3_PADDR	SCHIZO_PBM_A_MEM_PADDR + DISKA3_OFFSET
#define DISKA4_PADDR	SCHIZO_PBM_A_MEM_PADDR + DISKA4_OFFSET
#define DISKA5_PADDR	SCHIZO_PBM_A_MEM_PADDR + DISKA5_OFFSET
#define DISKA6_PADDR	SCHIZO_PBM_A_MEM_PADDR + DISKA6_OFFSET
#define DISKA7_PADDR	SCHIZO_PBM_A_MEM_PADDR + DISKA7_OFFSET
#define DISKA8_PADDR	SCHIZO_PBM_A_MEM_PADDR + DISKA8_OFFSET
#define DISKA9_PADDR	SCHIZO_PBM_A_MEM_PADDR + DISKA9_OFFSET
#define DISKA10_PADDR	SCHIZO_PBM_A_MEM_PADDR + DISKA10_OFFSET
#define DISKA11_PADDR	SCHIZO_PBM_A_MEM_PADDR + DISKA11_OFFSET
#define DISKA12_PADDR	SCHIZO_PBM_A_MEM_PADDR + DISKA12_OFFSET
#define DISKA13_PADDR	SCHIZO_PBM_A_MEM_PADDR + DISKA13_OFFSET
#define DISKA14_PADDR	SCHIZO_PBM_A_MEM_PADDR + DISKA14_OFFSET
#define DISKA15_PADDR	SCHIZO_PBM_A_MEM_PADDR + DISKA15_OFFSET
#define DISKA16_PADDR	SCHIZO_PBM_A_MEM_PADDR + DISKA16_OFFSET
#define DISKA17_PADDR	SCHIZO_PBM_A_MEM_PADDR + DISKA17_OFFSET
#define DISKA18_PADDR	SCHIZO_PBM_A_MEM_PADDR + DISKA18_OFFSET
#define DISKA19_PADDR	SCHIZO_PBM_A_MEM_PADDR + DISKA19_OFFSET
#define DISKA20_PADDR	SCHIZO_PBM_A_MEM_PADDR + DISKA20_OFFSET
#define DISKA21_PADDR	SCHIZO_PBM_A_MEM_PADDR + DISKA21_OFFSET
#define DISKA22_PADDR	SCHIZO_PBM_A_MEM_PADDR + DISKA22_OFFSET
#define DISKA23_PADDR	SCHIZO_PBM_A_MEM_PADDR + DISKA23_OFFSET
#define DISKA24_PADDR	SCHIZO_PBM_A_MEM_PADDR + DISKA24_OFFSET
/* 25 disks on bus B */
#define DISKB0_PADDR	SCHIZO_PBM_B_MEM_PADDR + DISKB0_OFFSET
#define DISKB1_PADDR	SCHIZO_PBM_B_MEM_PADDR + DISKB1_OFFSET
#define DISKB2_PADDR	SCHIZO_PBM_B_MEM_PADDR + DISKB2_OFFSET
#define DISKB3_PADDR	SCHIZO_PBM_B_MEM_PADDR + DISKB3_OFFSET
#define DISKB4_PADDR	SCHIZO_PBM_B_MEM_PADDR + DISKB4_OFFSET
#define DISKB5_PADDR	SCHIZO_PBM_B_MEM_PADDR + DISKB5_OFFSET
#define DISKB6_PADDR	SCHIZO_PBM_B_MEM_PADDR + DISKB6_OFFSET
#define DISKB7_PADDR	SCHIZO_PBM_B_MEM_PADDR + DISKB7_OFFSET
#define DISKB8_PADDR	SCHIZO_PBM_B_MEM_PADDR + DISKB8_OFFSET
#define DISKB9_PADDR	SCHIZO_PBM_B_MEM_PADDR + DISKB9_OFFSET
#define DISKB10_PADDR	SCHIZO_PBM_B_MEM_PADDR + DISKB10_OFFSET
#define DISKB11_PADDR	SCHIZO_PBM_B_MEM_PADDR + DISKB11_OFFSET
#define DISKB12_PADDR	SCHIZO_PBM_B_MEM_PADDR + DISKB12_OFFSET
#define DISKB13_PADDR	SCHIZO_PBM_B_MEM_PADDR + DISKB13_OFFSET
#define DISKB14_PADDR	SCHIZO_PBM_B_MEM_PADDR + DISKB14_OFFSET
#define DISKB15_PADDR	SCHIZO_PBM_B_MEM_PADDR + DISKB15_OFFSET
#define DISKB16_PADDR	SCHIZO_PBM_B_MEM_PADDR + DISKB16_OFFSET
#define DISKB17_PADDR	SCHIZO_PBM_B_MEM_PADDR + DISKB17_OFFSET
#define DISKB18_PADDR	SCHIZO_PBM_B_MEM_PADDR + DISKB18_OFFSET
#define DISKB19_PADDR	SCHIZO_PBM_B_MEM_PADDR + DISKB19_OFFSET
#define DISKB20_PADDR	SCHIZO_PBM_B_MEM_PADDR + DISKB20_OFFSET
#define DISKB21_PADDR	SCHIZO_PBM_B_MEM_PADDR + DISKB21_OFFSET


#define PCIA_SCSI00_PADDR    SCHIZO_PBM_A_MEM_PADDR + PCIA_SCSI00_OFFSET_1
#define PCIA_SCSI01_PADDR    SCHIZO_PBM_A_MEM_PADDR + PCIA_SCSI01_OFFSET_1
#define PCIA_SCSI02_PADDR    SCHIZO_PBM_A_MEM_PADDR + PCIA_SCSI02_OFFSET_1
#define PCIA_SCSI03_PADDR    SCHIZO_PBM_A_MEM_PADDR + PCIA_SCSI03_OFFSET_1
#define PCIA_SCSI04_PADDR    SCHIZO_PBM_A_MEM_PADDR + PCIA_SCSI04_OFFSET_1
#define PCIA_SCSI05_PADDR    SCHIZO_PBM_A_MEM_PADDR + PCIA_SCSI05_OFFSET_1
#define PCIA_SCSI06_PADDR    SCHIZO_PBM_A_MEM_PADDR + PCIA_SCSI06_OFFSET_1
#define PCIA_SCSI07_PADDR    SCHIZO_PBM_A_MEM_PADDR + PCIA_SCSI07_OFFSET_1
#define PCIA_SCSI08_PADDR    SCHIZO_PBM_A_MEM_PADDR + PCIA_SCSI08_OFFSET_1
#define PCIA_SCSI09_PADDR    SCHIZO_PBM_A_MEM_PADDR + PCIA_SCSI09_OFFSET_1
#define PCIA_SCSI10_PADDR    SCHIZO_PBM_A_MEM_PADDR + PCIA_SCSI10_OFFSET_1
#define PCIA_SCSI11_PADDR    SCHIZO_PBM_A_MEM_PADDR + PCIA_SCSI11_OFFSET_1
#define PCIA_SCSI12_PADDR    SCHIZO_PBM_A_MEM_PADDR + PCIA_SCSI12_OFFSET_1
#define PCIA_SCSI13_PADDR    SCHIZO_PBM_A_MEM_PADDR + PCIA_SCSI13_OFFSET_1
#define PCIA_SCSI14_PADDR    SCHIZO_PBM_A_MEM_PADDR + PCIA_SCSI14_OFFSET_1
#define PCIA_SCSI15_PADDR    SCHIZO_PBM_A_MEM_PADDR + PCIA_SCSI15_OFFSET_1
#define PCIA_SCSI16_PADDR    SCHIZO_PBM_A_MEM_PADDR + PCIA_SCSI16_OFFSET_1
#define PCIA_SCSI17_PADDR    SCHIZO_PBM_A_MEM_PADDR + PCIA_SCSI17_OFFSET_1
#define PCIA_SCSI18_PADDR    SCHIZO_PBM_A_MEM_PADDR + PCIA_SCSI18_OFFSET_1
#define PCIA_SCSI19_PADDR    SCHIZO_PBM_A_MEM_PADDR + PCIA_SCSI19_OFFSET_1
#define PCIA_SCSI20_PADDR    SCHIZO_PBM_A_MEM_PADDR + PCIA_SCSI20_OFFSET_1
#define PCIA_SCSI21_PADDR    SCHIZO_PBM_A_MEM_PADDR + PCIA_SCSI21_OFFSET_1
#define PCIA_SCSI22_PADDR    SCHIZO_PBM_A_MEM_PADDR + PCIA_SCSI22_OFFSET_1
#define PCIA_SCSI23_PADDR    SCHIZO_PBM_A_MEM_PADDR + PCIA_SCSI23_OFFSET_1
#define PCIA_SCSI24_PADDR    SCHIZO_PBM_A_MEM_PADDR + PCIA_SCSI24_OFFSET_1

/* pci bus B */

#define PCIB_SCSI00_PADDR    SCHIZO_PBM_B_MEM_PADDR + PCIB_SCSI00_OFFSET_1
#define PCIB_SCSI01_PADDR    SCHIZO_PBM_B_MEM_PADDR + PCIB_SCSI01_OFFSET_1
#define PCIB_SCSI02_PADDR    SCHIZO_PBM_B_MEM_PADDR + PCIB_SCSI02_OFFSET_1
#define PCIB_SCSI03_PADDR    SCHIZO_PBM_B_MEM_PADDR + PCIB_SCSI03_OFFSET_1
#define PCIB_SCSI04_PADDR    SCHIZO_PBM_B_MEM_PADDR + PCIB_SCSI04_OFFSET_1
#define PCIB_SCSI05_PADDR    SCHIZO_PBM_B_MEM_PADDR + PCIB_SCSI05_OFFSET_1
#define PCIB_SCSI06_PADDR    SCHIZO_PBM_B_MEM_PADDR + PCIB_SCSI06_OFFSET_1
#define PCIB_SCSI07_PADDR    SCHIZO_PBM_B_MEM_PADDR + PCIB_SCSI07_OFFSET_1
#define PCIB_SCSI08_PADDR    SCHIZO_PBM_B_MEM_PADDR + PCIB_SCSI08_OFFSET_1
#define PCIB_SCSI09_PADDR    SCHIZO_PBM_B_MEM_PADDR + PCIB_SCSI09_OFFSET_1
#define PCIB_SCSI10_PADDR    SCHIZO_PBM_B_MEM_PADDR + PCIB_SCSI10_OFFSET_1
#define PCIB_SCSI11_PADDR    SCHIZO_PBM_B_MEM_PADDR + PCIB_SCSI11_OFFSET_1
#define PCIB_SCSI12_PADDR    SCHIZO_PBM_B_MEM_PADDR + PCIB_SCSI12_OFFSET_1
#define PCIB_SCSI13_PADDR    SCHIZO_PBM_B_MEM_PADDR + PCIB_SCSI13_OFFSET_1
#define PCIB_SCSI14_PADDR    SCHIZO_PBM_B_MEM_PADDR + PCIB_SCSI14_OFFSET_1
#define PCIB_SCSI15_PADDR    SCHIZO_PBM_B_MEM_PADDR + PCIB_SCSI15_OFFSET_1
#define PCIB_SCSI16_PADDR    SCHIZO_PBM_B_MEM_PADDR + PCIB_SCSI16_OFFSET_1
#define PCIB_SCSI17_PADDR    SCHIZO_PBM_B_MEM_PADDR + PCIB_SCSI17_OFFSET_1
#define PCIB_SCSI18_PADDR    SCHIZO_PBM_B_MEM_PADDR + PCIB_SCSI18_OFFSET_1
#define PCIB_SCSI19_PADDR    SCHIZO_PBM_B_MEM_PADDR + PCIB_SCSI19_OFFSET_1
#define PCIB_SCSI20_PADDR    SCHIZO_PBM_B_MEM_PADDR + PCIB_SCSI20_OFFSET_1
#define PCIB_SCSI21_PADDR    SCHIZO_PBM_B_MEM_PADDR + PCIB_SCSI21_OFFSET_1
#define PCIB_SCSI22_PADDR    SCHIZO_PBM_B_MEM_PADDR + PCIB_SCSI22_OFFSET_1
#define PCIB_SCSI23_PADDR    SCHIZO_PBM_B_MEM_PADDR + PCIB_SCSI23_OFFSET_1
#define PCIB_SCSI24_PADDR    SCHIZO_PBM_B_MEM_PADDR + PCIB_SCSI24_OFFSET_1



#define DISKB22_PADDR   SCHIZO_PBM_B_MEM_PADDR + DISKB22_OFFSET
#define DISKB23_PADDR   SCHIZO_PBM_B_MEM_PADDR + DISKB23_OFFSET
#define DISKB24_PADDR   SCHIZO_PBM_B_MEM_PADDR + DISKB24_OFFSET
 

/* FC (bus a) */
#define PCIA_FC00_PADDR    SCHIZO_PBM_A_MEM_PADDR + PCIA_FC00_OFFSET
#define PCIA_FC01_PADDR    SCHIZO_PBM_A_MEM_PADDR + PCIA_FC01_OFFSET
#define PCIA_FC02_PADDR    SCHIZO_PBM_A_MEM_PADDR + PCIA_FC02_OFFSET
#define PCIA_FC03_PADDR    SCHIZO_PBM_A_MEM_PADDR + PCIA_FC03_OFFSET


/* FC (bus b) */
#define PCIB_FC00_PADDR    SCHIZO_PBM_B_MEM_PADDR + PCIB_FC00_OFFSET
#define PCIB_FC01_PADDR    SCHIZO_PBM_B_MEM_PADDR + PCIB_FC01_OFFSET
#define PCIB_FC02_PADDR    SCHIZO_PBM_B_MEM_PADDR + PCIB_FC02_OFFSET


#define SCSI_CTRL_RSIZE_1       0x00100
#define SCSI_CTRL_RSIZE_2       0x00100
#define SCSI_CTRL_RSIZE_3       0x01000
#define SCSI_CTRL_RSIZE         0x02000
 


/*  serial on bus B*/
#define SCHIZO_PCISIMC_PADDR		SCHIZO_PBM_B_MEM_PADDR + PCISIMC_OFFSET

#define SCHIZO_PCI_A_CSRBASE_OFFSET	0x600000
#define SCHIZO_PCI_A_CSRBASE_PADDR	SAFARIBASE_PADDR + SCHIZO_PCI_A_CSRBASE_OFFSET
#define SCHIZO_PCI_B_CSRBASE_OFFSET	0x700000
#define SCHIZO_PCI_B_CSRBASE_PADDR	SAFARIBASE_PADDR + SCHIZO_PCI_B_CSRBASE_OFFSET

#define SAFARI_CSRBASE		0x400000
#define SAFARI_ERROR_BASE	0x410000
#define SAFARI_ERROR_BASE_PADDR	SAFARIBASE_PADDR + SAFARI_ERROR_BASE	
#define PCI_B_MEM_ADDR_MATCH	0x400060
#define PCI_B_MEM_ADDR_MASK	0x400068
#define PCI_B_CONFIG_ADDR_MATCH	0x400070
#define PCI_B_CONFIG_ADDR_MASK	0x400078
#define PCI_A_MEM_ADDR_MATCH	0x400040
#define PCI_A_MEM_ADDR_MASK	0x400048
#define PCI_A_CONFIG_ADDR_MATCH	0x400050
#define PCI_A_CONFIG_ADDR_MASK	0x400058



#define	PBM_A_CONFIG_RSIZE	0x8000
#define	PBM_A_CONFIG_VADDR	0xFFF00000
#define	PBM_B_CONFIG_RSIZE	0x8000
#define	PBM_B_CONFIG_VADDR	0xFFF08000


#define DISK_RSIZE	0x20

/* pcisimd (bus a) */
#define DISKA0_OFFSET	0x0000
#define DISKA0_VADDR	0xFFE00000


#define DISKA1_OFFSET	0x2000
#define DISKA1_VADDR	0xFFE02000
#define DISKA2_OFFSET	0x4000
#define DISKA2_VADDR	0xFFE04000
#define DISKA3_OFFSET	0x6000
#define DISKA3_VADDR	0xFFE06000
#define DISKA4_OFFSET	0x8000
#define DISKA4_VADDR	0xFFE08000
#define DISKA5_OFFSET	0xA000
#define DISKA5_VADDR	0xFFE0A000
#define DISKA6_OFFSET	0xC000
#define DISKA6_VADDR	0xFFE0C000
#define DISKA7_OFFSET	0xE000
#define DISKA7_VADDR	0xFFE0E000
#define DISKA8_OFFSET	0x10000
#define DISKA8_VADDR	0xFFE10000
#define DISKA9_OFFSET	0x12000
#define DISKA9_VADDR	0xFFE12000
#define DISKA10_OFFSET	0x14000
#define DISKA10_VADDR	0xFFE14000
#define DISKA11_OFFSET	0x16000
#define DISKA11_VADDR	0xFFE16000
#define DISKA12_OFFSET	0x18000
#define DISKA12_VADDR	0xFFE18000
#define DISKA13_OFFSET	0x1A000
#define DISKA13_VADDR	0xFFE1A000
#define DISKA14_OFFSET	0x1C000
#define DISKA14_VADDR	0xFFE1C000
#define DISKA15_OFFSET	0x1E000
#define DISKA15_VADDR	0xFFE1E000

#define DISKA16_OFFSET	0x20000
#define DISKA16_VADDR	0xFFE20000
#define DISKA17_OFFSET	0x22000
#define DISKA17_VADDR	0xFFE22000
#define DISKA18_OFFSET	0x24000
#define DISKA18_VADDR	0xFFE24000
#define DISKA19_OFFSET	0x26000
#define DISKA19_VADDR	0xFFE26000
#define DISKA20_OFFSET	0x28000
#define DISKA20_VADDR	0xFFE28000
#define DISKA21_OFFSET	0x2A000
#define DISKA21_VADDR	0xFFE2A000
#define DISKA22_OFFSET	0x2C000
#define DISKA22_VADDR	0xFFE2C000
#define DISKA23_OFFSET	0x2E000
#define DISKA23_VADDR	0xFFE2E000
#define DISKA24_OFFSET	0x30000
#define DISKA24_VADDR	0xFFE30000

/* pcisimd (bus b) */
#define DISKB0_OFFSET	0x0000
#define DISKB0_VADDR	0xFFE80000
#define DISKB1_OFFSET	0x2000
#define DISKB1_VADDR	0xFFE82000
#define DISKB2_OFFSET	0x4000
#define DISKB2_VADDR	0xFFE84000
#define DISKB3_OFFSET	0x6000
#define DISKB3_VADDR	0xFFE86000
#define DISKB4_OFFSET	0x8000
#define DISKB4_VADDR	0xFFE88000
#define DISKB5_OFFSET	0xA000
#define DISKB5_VADDR	0xFFE8A000
#define DISKB6_OFFSET	0xC000
#define DISKB6_VADDR	0xFFE8C000
#define DISKB7_OFFSET	0xE000
#define DISKB7_VADDR	0xFFE8E000
#define DISKB8_OFFSET	0x10000
#define DISKB8_VADDR	0xFFE90000
#define DISKB9_OFFSET	0x12000
#define DISKB9_VADDR	0xFFE92000
#define DISKB10_OFFSET	0x14000
#define DISKB10_VADDR	0xFFE94000
#define DISKB11_OFFSET	0x16000
#define DISKB11_VADDR	0xFFE96000
#define DISKB12_OFFSET	0x18000
#define DISKB12_VADDR	0xFFE98000
#define DISKB13_OFFSET	0x1A000
#define DISKB13_VADDR	0xFFE9A000
#define DISKB14_OFFSET	0x1C000
#define DISKB14_VADDR	0xFFE9C000
#define DISKB15_OFFSET	0x1E000
#define DISKB15_VADDR	0xFFE9E000

#define DISKB16_OFFSET	0x20000
#define DISKB16_VADDR	0xFFEA0000
#define DISKB17_OFFSET	0x22000
#define DISKB17_VADDR	0xFFEA2000
#define DISKB18_OFFSET	0x24000
#define DISKB18_VADDR	0xFFEA4000
#define DISKB19_OFFSET	0x26000
#define DISKB19_VADDR	0xFFEA6000
#define DISKB20_OFFSET	0x28000
#define DISKB20_VADDR	0xFFEA8000
#define DISKB21_OFFSET	0x2A000
#define DISKB21_VADDR	0xFFEAA000



/* scsi_ctrl (bus a) */


#define PCIA_SCSI00_OFFSET_1         0x0000
#define PCIA_SCSI00_OFFSET_2         0x0100 
#define PCIA_SCSI00_OFFSET_3         0x1000 
#define PCIA_SCSI00_VADDR            0xffe00000 

#define PCIA_SCSI01_OFFSET_1         0x2000 
#define PCIA_SCSI01_OFFSET_2         0x2100 
#define PCIA_SCSI01_OFFSET_3         0x3000 
#define PCIA_SCSI01_VADDR            0xffe02000 

#define PCIA_SCSI02_OFFSET_1         0x4000 
#define PCIA_SCSI02_OFFSET_2         0x4100 
#define PCIA_SCSI02_OFFSET_3         0x5000 
#define PCIA_SCSI02_VADDR            0xffe04000 

#define PCIA_SCSI03_OFFSET_1         0x6000 
#define PCIA_SCSI03_OFFSET_2         0x6100 
#define PCIA_SCSI03_OFFSET_3         0x7000 
#define PCIA_SCSI03_VADDR            0xffe06000 

#define PCIA_SCSI04_OFFSET_1         0x8000 
#define PCIA_SCSI04_OFFSET_2         0x8100 
#define PCIA_SCSI04_OFFSET_3         0x9000 
#define PCIA_SCSI04_VADDR            0xffe08000 

#define PCIA_SCSI05_OFFSET_1         0xa000 
#define PCIA_SCSI05_OFFSET_2         0xa100 
#define PCIA_SCSI05_OFFSET_3         0xb000 
#define PCIA_SCSI05_VADDR            0xffe0a000 

#define PCIA_SCSI06_OFFSET_1         0xc000 
#define PCIA_SCSI06_OFFSET_2         0xc100 
#define PCIA_SCSI06_OFFSET_3         0xd000 
#define PCIA_SCSI06_VADDR            0xffe0c000 

#define PCIA_SCSI07_OFFSET_1         0xe000 
#define PCIA_SCSI07_OFFSET_2         0xe100 
#define PCIA_SCSI07_OFFSET_3         0xf000 
#define PCIA_SCSI07_VADDR            0xffe0e000 

#define PCIA_SCSI08_OFFSET_1         0x10000 
#define PCIA_SCSI08_OFFSET_2         0x10100 
#define PCIA_SCSI08_OFFSET_3         0x11000 
#define PCIA_SCSI08_VADDR            0xffe10000 

#define PCIA_SCSI09_OFFSET_1         0x12000 
#define PCIA_SCSI09_OFFSET_2         0x12100 
#define PCIA_SCSI09_OFFSET_3         0x13000 
#define PCIA_SCSI09_VADDR            0xffe12000 

#define PCIA_SCSI10_OFFSET_1         0x14000 
#define PCIA_SCSI10_OFFSET_2         0x14100 
#define PCIA_SCSI10_OFFSET_3         0x15000 
#define PCIA_SCSI10_VADDR            0xffe14000 

#define PCIA_SCSI11_OFFSET_1         0x16000 
#define PCIA_SCSI11_OFFSET_2         0x16100 
#define PCIA_SCSI11_OFFSET_3         0x17000 
#define PCIA_SCSI11_VADDR            0xffe16000 

#define PCIA_SCSI12_OFFSET_1         0x18000 
#define PCIA_SCSI12_OFFSET_2         0x18100 
#define PCIA_SCSI12_OFFSET_3         0x19000 
#define PCIA_SCSI12_VADDR            0xffe18000 

#define PCIA_SCSI13_OFFSET_1         0x1a000 
#define PCIA_SCSI13_OFFSET_2         0x1a100 
#define PCIA_SCSI13_OFFSET_3         0x1b000 
#define PCIA_SCSI13_VADDR            0xffe1a000 

#define PCIA_SCSI14_OFFSET_1         0x1c000 
#define PCIA_SCSI14_OFFSET_2         0x1c100 
#define PCIA_SCSI14_OFFSET_3         0x1d000 
#define PCIA_SCSI14_VADDR            0xffe1c000 

#define PCIA_SCSI15_OFFSET_1         0x1e000 
#define PCIA_SCSI15_OFFSET_2         0x1e100 
#define PCIA_SCSI15_OFFSET_3         0x1f000 
#define PCIA_SCSI15_VADDR            0xffe1e000 

#define PCIA_SCSI16_OFFSET_1         0x20000 
#define PCIA_SCSI16_OFFSET_2         0x20100 
#define PCIA_SCSI16_OFFSET_3         0x21000 
#define PCIA_SCSI16_VADDR            0xffe20000 

#define PCIA_SCSI17_OFFSET_1         0x22000 
#define PCIA_SCSI17_OFFSET_2         0x22100 
#define PCIA_SCSI17_OFFSET_3         0x23000 
#define PCIA_SCSI17_VADDR            0xffe22000 

#define PCIA_SCSI18_OFFSET_1         0x24000 
#define PCIA_SCSI18_OFFSET_2         0x24100 
#define PCIA_SCSI18_OFFSET_3         0x25000 
#define PCIA_SCSI18_VADDR            0xffe24000 

#define PCIA_SCSI19_OFFSET_1         0x26000 
#define PCIA_SCSI19_OFFSET_2         0x26100 
#define PCIA_SCSI19_OFFSET_3         0x27000 
#define PCIA_SCSI19_VADDR            0xffe26000 

#define PCIA_SCSI20_OFFSET_1         0x28000 
#define PCIA_SCSI20_OFFSET_2         0x28100 
#define PCIA_SCSI20_OFFSET_3         0x29000 
#define PCIA_SCSI20_VADDR            0xffe28000 

#define PCIA_SCSI21_OFFSET_1         0x2a000 
#define PCIA_SCSI21_OFFSET_2         0x2a100 
#define PCIA_SCSI21_OFFSET_3         0x2b000 
#define PCIA_SCSI21_VADDR            0xffe2a000 

#define PCIA_SCSI22_OFFSET_1         0x2c000 
#define PCIA_SCSI22_OFFSET_2         0x2c100 
#define PCIA_SCSI22_OFFSET_3         0x2d000 
#define PCIA_SCSI22_VADDR            0xffe2c000 

#define PCIA_SCSI23_OFFSET_1         0x2e000 
#define PCIA_SCSI23_OFFSET_2         0x2e100 
#define PCIA_SCSI23_OFFSET_3         0x2f000 
#define PCIA_SCSI23_VADDR            0xffe2e000 

#define PCIA_SCSI24_OFFSET_1         0x30000 
#define PCIA_SCSI24_OFFSET_2         0x30100 
#define PCIA_SCSI24_OFFSET_3         0x31000 
#define PCIA_SCSI24_VADDR            0xffe30000 


/* scsi_ctrl (bus b) */


#define PCIB_SCSI00_OFFSET_1         0x0000 
#define PCIB_SCSI00_OFFSET_2         0x0100 
#define PCIB_SCSI00_OFFSET_3         0x1000 
#define PCIB_SCSI00_VADDR            0xffe80000 

#define PCIB_SCSI01_OFFSET_1         0x2000 
#define PCIB_SCSI01_OFFSET_2         0x2100 
#define PCIB_SCSI01_OFFSET_3         0x3000 
#define PCIB_SCSI01_VADDR            0xffe82000 

#define PCIB_SCSI02_OFFSET_1         0x4000 
#define PCIB_SCSI02_OFFSET_2         0x4100 
#define PCIB_SCSI02_OFFSET_3         0x5000 
#define PCIB_SCSI02_VADDR            0xffe84000 

#define PCIB_SCSI03_OFFSET_1         0x6000 
#define PCIB_SCSI03_OFFSET_2         0x6100 
#define PCIB_SCSI03_OFFSET_3         0x7000 
#define PCIB_SCSI03_VADDR            0xffe86000 

#define PCIB_SCSI04_OFFSET_1         0x8000 
#define PCIB_SCSI04_OFFSET_2         0x8100 
#define PCIB_SCSI04_OFFSET_3         0x9000 
#define PCIB_SCSI04_VADDR            0xffe88000 

#define PCIB_SCSI05_OFFSET_1         0xa000 
#define PCIB_SCSI05_OFFSET_2         0xa100 
#define PCIB_SCSI05_OFFSET_3         0xb000 
#define PCIB_SCSI05_VADDR            0xffe8a000 

#define PCIB_SCSI06_OFFSET_1         0xc000 
#define PCIB_SCSI06_OFFSET_2         0xc100 
#define PCIB_SCSI06_OFFSET_3         0xd000 
#define PCIB_SCSI06_VADDR            0xffe8c000 

#define PCIB_SCSI07_OFFSET_1         0xe000 
#define PCIB_SCSI07_OFFSET_2         0xe100 
#define PCIB_SCSI07_OFFSET_3         0xf000 
#define PCIB_SCSI07_VADDR            0xffe8e000 

#define PCIB_SCSI08_OFFSET_1         0x10000 
#define PCIB_SCSI08_OFFSET_2         0x10100 
#define PCIB_SCSI08_OFFSET_3         0x11000 
#define PCIB_SCSI08_VADDR            0xffe90000 

#define PCIB_SCSI09_OFFSET_1         0x12000 
#define PCIB_SCSI09_OFFSET_2         0x12100 
#define PCIB_SCSI09_OFFSET_3         0x13000 
#define PCIB_SCSI09_VADDR            0xffe92000 

#define PCIB_SCSI10_OFFSET_1         0x14000 
#define PCIB_SCSI10_OFFSET_2         0x14100 
#define PCIB_SCSI10_OFFSET_3         0x15000 
#define PCIB_SCSI10_VADDR            0xffe94000 

#define PCIB_SCSI11_OFFSET_1         0x16000 
#define PCIB_SCSI11_OFFSET_2         0x16100 
#define PCIB_SCSI11_OFFSET_3         0x17000 
#define PCIB_SCSI11_VADDR            0xffe96000 

#define PCIB_SCSI12_OFFSET_1         0x18000 
#define PCIB_SCSI12_OFFSET_2         0x18100 
#define PCIB_SCSI12_OFFSET_3         0x19000 
#define PCIB_SCSI12_VADDR            0xffe98000 

#define PCIB_SCSI13_OFFSET_1         0x1a000 
#define PCIB_SCSI13_OFFSET_2         0x1a100 
#define PCIB_SCSI13_OFFSET_3         0x1b000 
#define PCIB_SCSI13_VADDR            0xffe9a000 

#define PCIB_SCSI14_OFFSET_1         0x1c000 
#define PCIB_SCSI14_OFFSET_2         0x1c100 
#define PCIB_SCSI14_OFFSET_3         0x1d000 
#define PCIB_SCSI14_VADDR            0xffe9c000 

#define PCIB_SCSI15_OFFSET_1         0x1e000 
#define PCIB_SCSI15_OFFSET_2         0x1e100 
#define PCIB_SCSI15_OFFSET_3         0x1f000 
#define PCIB_SCSI15_VADDR            0xffe9e000 

#define PCIB_SCSI16_OFFSET_1         0x20000 
#define PCIB_SCSI16_OFFSET_2         0x20100 
#define PCIB_SCSI16_OFFSET_3         0x21000 
#define PCIB_SCSI16_VADDR            0xffea0000 

#define PCIB_SCSI17_OFFSET_1         0x22000 
#define PCIB_SCSI17_OFFSET_2         0x22100 
#define PCIB_SCSI17_OFFSET_3         0x23000 
#define PCIB_SCSI17_VADDR            0xffea2000 

#define PCIB_SCSI18_OFFSET_1         0x24000 
#define PCIB_SCSI18_OFFSET_2         0x24100 
#define PCIB_SCSI18_OFFSET_3         0x25000 
#define PCIB_SCSI18_VADDR            0xffea4000 

#define PCIB_SCSI19_OFFSET_1         0x26000 
#define PCIB_SCSI19_OFFSET_2         0x26100 
#define PCIB_SCSI19_OFFSET_3         0x27000 
#define PCIB_SCSI19_VADDR            0xffea6000 

#define PCIB_SCSI20_OFFSET_1         0x28000 
#define PCIB_SCSI20_OFFSET_2         0x28100 
#define PCIB_SCSI20_OFFSET_3         0x29000 
#define PCIB_SCSI20_VADDR            0xffea8000 

#define PCIB_SCSI21_OFFSET_1         0x2a000 
#define PCIB_SCSI21_OFFSET_2         0x2a100 
#define PCIB_SCSI21_OFFSET_3         0x2b000 
#define PCIB_SCSI21_VADDR            0xffeaa000 

#define PCIB_SCSI22_OFFSET_1         0x2c000
#define PCIB_SCSI22_OFFSET_2         0x2c100
#define PCIB_SCSI22_OFFSET_3         0x2d000
#define PCIB_SCSI22_VADDR            0xffeac000

#define PCIB_SCSI23_OFFSET_1         0x2e000
#define PCIB_SCSI23_OFFSET_2         0x2e100
#define PCIB_SCSI23_OFFSET_3         0x2f000
#define PCIB_SCSI23_VADDR            0xffeae000

#define PCIB_SCSI24_OFFSET_1         0x30000
#define PCIB_SCSI24_OFFSET_2         0x30100
#define PCIB_SCSI24_OFFSET_3         0x31000
#define PCIB_SCSI24_VADDR            0xffeb0000



/* FC (bus A) */
#define FC_CTRL_RSIZE              0x500

#define PCIA_FC00_OFFSET           0x0000
#define PCIA_FC00_VADDR            0xffe00000 

#define PCIA_FC01_OFFSET           0x2000 
#define PCIA_FC01_VADDR            0xffe02000 

#define PCIA_FC02_OFFSET           0x4000 
#define PCIA_FC02_VADDR            0xffe04000 

#define PCIA_FC03_OFFSET           0x6000 
#define PCIA_FC03_VADDR            0xffe06000 

#define PCIA_FC04_OFFSET             0x8000
#define PCIA_FC04_VADDR              0xffe08000

#define PCIA_FC05_OFFSET             0xa000
#define PCIA_FC05_VADDR              0xffe0a000

#define PCIA_FC06_OFFSET         0xc000
#define PCIA_FC06_VADDR            0xffe0c000

#define PCIA_FC07_OFFSET         0xe000
#define PCIA_FC07_VADDR            0xffe0e000

#define PCIA_FC08_OFFSET         0x10000
#define PCIA_FC08_VADDR            0xffe10000

#define PCIA_FC09_OFFSET         0x12000
#define PCIA_FC09_VADDR            0xffe12000

#define PCIA_FC10_OFFSET         0x14000
#define PCIA_FC10_VADDR            0xffe14000

#define PCIA_FC11_OFFSET         0x16000
#define PCIA_FC11_VADDR            0xffe16000

#define PCIA_FC12_OFFSET         0x18000
#define PCIA_FC12_VADDR            0xffe18000

#define PCIA_FC13_OFFSET         0x1a000
#define PCIA_FC13_VADDR            0xffe1a000

#define PCIA_FC14_OFFSET         0x1c000
#define PCIA_FC14_VADDR            0xffe1c000

#define PCIA_FC15_OFFSET         0x1e000
#define PCIA_FC15_VADDR            0xffe1e000

#define PCIA_FC16_OFFSET         0x20000
#define PCIA_FC16_VADDR            0xffe20000

#define PCIA_FC17_OFFSET         0x22000
#define PCIA_FC17_VADDR            0xffe22000

#define PCIA_FC18_OFFSET         0x24000
#define PCIA_FC18_VADDR            0xffe24000

#define PCIA_FC19_OFFSET         0x26000
#define PCIA_FC19_VADDR            0xffe26000

#define PCIA_FC20_OFFSET         0x28000
#define PCIA_FC20_VADDR            0xffe28000

#define PCIA_FC21_OFFSET         0x2a000
#define PCIA_FC21_VADDR            0xffe2a000

#define PCIA_FC22_OFFSET         0x2c000
#define PCIA_FC22_VADDR            0xffe2c000

#define PCIA_FC23_OFFSET         0x2e000
#define PCIA_FC23_VADDR            0xffe2e000

#define PCIA_FC24_OFFSET         0x30000
#define PCIA_FC24_VADDR            0xffe30000

/* FC (bus b) */

#define PCIB_FC00_OFFSET         0x0000 
#define PCIB_FC00_VADDR          0xffe80000

#define PCIB_FC01_OFFSET         0x2000 
#define PCIB_FC01_VADDR          0xffe82000

#define PCIB_FC02_OFFSET         0x4000 
#define PCIB_FC02_VADDR          0xffe84000

#define PCIB_FC03_OFFSET         0x6000
#define PCIB_FC03_VADDR          0xffe86000

#define PCIB_FC04_OFFSET         0x8000
#define PCIB_FC04_VADDR          0xffe88000

#define PCIB_FC05_OFFSET         0xa000
#define PCIB_FC05_VADDR          0xffe8a000

#define PCIB_FC06_OFFSET         0xc000
#define PCIB_FC06_VADDR          0xffe8c000

#define PCIB_FC07_OFFSET         0xe000
#define PCIB_FC07_VADDR          0xffe8e000

#define PCIB_FC08_OFFSET         0x10000
#define PCIB_FC08_VADDR          0xffe90000

#define PCIB_FC09_OFFSET         0x12000
#define PCIB_FC09_VADDR          0xffe92000

#define PCIB_FC10_OFFSET         0x14000
#define PCIB_FC10_VADDR          0xffe94000

#define PCIB_FC11_OFFSET         0x16000
#define PCIB_FC11_VADDR          0xffe96000

#define PCIB_FC12_OFFSET         0x18000
#define PCIB_FC12_VADDR          0xffe98000

#define PCIB_FC13_OFFSET         0x1a000
#define PCIB_FC13_VADDR          0xffe9a000

#define PCIB_FC14_OFFSET           0x1c000
#define PCIB_FC14_VADDR            0xffe9c000

#define PCIB_FC15_OFFSET           0x1e000
#define PCIB_FC15_VADDR            0xffe9e000

#define PCIB_FC16_OFFSET           0x20000
#define PCIB_FC16_VADDR            0xffea0000

#define PCIB_FC17_OFFSET           0x22000
#define PCIB_FC17_VADDR            0xffea2000

#define PCIB_FC18_OFFSET           0x24000
#define PCIB_FC18_VADDR            0xffea4000

#define PCIB_FC19_OFFSET           0x26000
#define PCIB_FC19_VADDR            0xffea6000

#define PCIB_FC20_OFFSET           0x28000
#define PCIB_FC20_VADDR            0xffea8000

#define PCIB_FC21_OFFSET           0x2a000
#define PCIB_FC21_VADDR            0xffeaa000

#define PCIB_FC22_OFFSET           0x2c000
#define PCIB_FC22_VADDR            0xffeac000

#define PCIB_FC23_OFFSET           0x2e000
#define PCIB_FC23_VADDR            0xffeae000

#define PCIB_FC24_OFFSET           0x30000
#define PCIB_FC24_VADDR            0xffeb0000

#define DISKB22_OFFSET  0x2C000
#define DISKB22_VADDR   0xFFEAC000
#define DISKB23_OFFSET  0x2E000
#define DISKB23_VADDR   0xFFEAE000
#define DISKB24_OFFSET  0x30000
#define DISKB24_VADDR   0xFFEB0000

/* bootbus controller */
#define BOOTBUS_CTRL_OFFSET          0x90000
#define BOOTBUS_CTRL_RSIZE           0x8000000


/* pcisimc (bus b) */
#define PCISIMC_OFFSET          0x32000
#define PCISIMC_RSIZE		0x1000
#define PCISIMC_VADDR		0xFFFC0000

/* ge0 (bus b) */
#define GE0_OFFSET          	0x36000
#define GE0_RSIZE           	0xA000

#define GE1_OFFSET          	0x40000
#define GE1_RSIZE           	0xA000

#define GE2_OFFSET              0x4A000
#define GE2_RSIZE               0xA000

#define GE3_OFFSET              0x54000
#define GE3_RSIZE               0xA000

#define GE4_OFFSET              0x5e000
#define GE4_RSIZE               0xA000
 
#define GE5_OFFSET              0x68000
#define GE5_RSIZE               0xA000

#define GE6_OFFSET              0x72000
#define GE6_RSIZE               0xA000
 
#define GE7_OFFSET              0x7c000
#define GE7_RSIZE               0xA000

#define GE8_OFFSET              0x86000
#define GE8_RSIZE               0xA000

#define GE9_OFFSET              0x90000
#define GE9_RSIZE               0xA000

#define GE10_OFFSET             0x9A000
#define GE10_RSIZE              0xA000

#define GE11_OFFSET             0xA4000
#define GE11_RSIZE              0xA000

#define GE12_OFFSET             0xAE000
#define GE12_RSIZE              0xA000

#define GE13_OFFSET             0xB8000
#define GE13_RSIZE              0xA000

#define GE14_OFFSET             0xC2000
#define GE14_RSIZE              0xA000

#define GE15_OFFSET             0xCC000
#define GE15_RSIZE              0xA000


/* ge (bus A) */
#define GE0_PCIA_OFFSET        	0x36000
#define GE0_PCIA_RSIZE         	0xA000

#define GE1_PCIA_OFFSET        	0x40000
#define GE1_PCIA_RSIZE         	0xA000

#define GE2_PCIA_OFFSET         0x4A000
#define GE2_PCIA_RSIZE          0xA000

#define GE3_PCIA_OFFSET         0x54000
#define GE3_PCIA_RSIZE          0xA000

#define GE4_PCIA_OFFSET         0x5e000
#define GE4_PCIA_RSIZE          0xA000
 
#define GE5_PCIA_OFFSET         0x68000
#define GE5_PCIA_RSIZE          0xA000

#define GE6_PCIA_OFFSET         0x72000
#define GE6_PCIA_RSIZE          0xA000

#define GE7_PCIA_OFFSET         0x7c000
#define GE7_PCIA_RSIZE          0xA000

#define GE8_PCIA_OFFSET         0x86000
#define GE8_PCIA_RSIZE          0xA000

#define GE9_PCIA_OFFSET         0x90000
#define GE9_PCIA_RSIZE          0xA000

#define GE10_PCIA_OFFSET        0x9A000
#define GE10_PCIA_RSIZE         0xA000

#define GE11_PCIA_OFFSET        0xA4000
#define GE11_PCIA_RSIZE         0xA000

#define GE12_PCIA_OFFSET        0xAE000
#define GE12_PCIA_RSIZE         0xA000

#define GE13_PCIA_OFFSET        0xB8000
#define GE13_PCIA_RSIZE         0xA000

#define GE14_PCIA_OFFSET        0xC2000
#define GE14_PCIA_RSIZE         0xA000

#define GE15_PCIA_OFFSET        0xCC000
#define GE15_PCIA_RSIZE         0xA000


#define CE0_OFFSET              0x86000 
#define CE0_RSIZE               0xA000

/* ll (bus b) */
#define LL_OFFSET               0x34000
#define LL_RSIZE                0x2000

/* bid (bus a) */
#define BID_OFFSET              0x32000
#define BID_RSIZE               0x2000

/* superio rtc (bus a) */
#define RTC_OFFSET              0x34000
#define RTC_RSIZE               0x2000
#define RTC_PADDR               (SCHIZO_PBM_A_MEM_PADDR + RTC_OFFSET)
#define RTC_VADDR               0xfffc2000

/* fakeprom base vaddr */
#define MONSTART		0xffd00000

/* vpt root page paddr */
#define VPTROOT_PA		0x10000		/* was 0x2000 started at 8K, which moved to 0x10000 due to more mem reserved to dev tree to be passed down */

#endif /* _ADDRESS_H */
